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low voltage, 1.15 v to 5.5 v, 4-channel, bidirectional logic level translator adg3304 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features bidirectional level translation operates from 1.15 v to 5.5 v low quiescent current < 5 a no direction pin applications spi?, microwire? level translation low voltage asic level translation smart card readers cell phones and cell phone cradles portable communications devices telecommunications equipment network switches and routers storage systems (san/nas) computing/server applications gps portable pos systems low cost serial interfaces functional block diagram a1 y1 gnd v ccy v cca en a4 y4 a3 y3 a2 y2 04860-001 figure 1. general description the adg3304 is a bidirectional logic level translator that con- tains four bidirectional channels. it can be used in multivoltage digital system applications, such as data transfer, between a low voltage digital signal processing controller and a higher voltage device using spi and microwire interfaces. the internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction in which the translation takes place. the voltage applied to v cca sets the logic levels on the a side of the device, while v ccy sets the levels on the y side. for proper operation, v cca must always be less than v ccy . the v cca -com- patible logic signals applied to the a side of the device appear as v ccy -compatible levels on the y side. similarly, v ccy -compatible logic levels applied to the y side of the device appear as v cca - compatible logic levels on the a side. the enable pin (en) provides three-state operation on both the a side and the y side pins. when the en pin is pulled low, the terminals on both sides of the device are in the high impedance state. the en pin is referred to the v cca supply voltage and driven high for normal operation. the adg3304 is available in compact 14-lead tssop, 12-ball wlcsp, and 20-lead lfcsp. it is guaranteed to operate over the 1.15 v to 5.5 v supply voltage range. product highlights 1. bidirectional level translation. 2. fully guaranteed over the 1.15 v to 5.5 v supply range. 3. no direction pin. 4. available in 14-lead tssop, 12-ball wlcsp, and 20-lead lfcsp.
adg3304 rev. b | page 2 of 20 table of contents specifications..................................................................................... 3 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 test circuits..................................................................................... 12 terminology .................................................................................... 15 theory of operation ...................................................................... 16 level translator architecture ................................................... 16 input driving requirements..................................................... 16 output load requirements ...................................................... 16 enable operation ....................................................................... 16 power supplies ............................................................................ 16 data rate ..................................................................................... 17 applications..................................................................................... 18 layout guidelines....................................................................... 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 20 revision history 12/05rev. a to rev. b changes to table 1............................................................................ 3 changes to table 2............................................................................ 6 changes to figure 3 and table 4..................................................... 7 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 21 6/05rev. 0 to rev. a added lfcsp package.......................................................universal 1/05revision 0: initial version
adg3304 rev. b | page 3 of 20 specifications v ccy = 1.65 v to 5.5 v, v cca = 1.15 v to v ccy , gnd = 0 v, t a = 25c. all specifications t min to t max , unless otherwise noted. table 1. b version 1 parameter symbol test conditions/comments min typ max unit logic inputs/outputs a side input high voltage 2 v iha v cca = 1.15 v v cca ? 0.3 v v iha v cca = 1.2 v to 5.5 v v cca ? 0.4 input low voltage 2 v ila 0.4 v output high voltage v oha v y = v ccy , i oh = 20 a, see figure 29 v cca ? 0.4 v output low voltage v ola v y = 0 v, i ol = 20 a, see figure 29 0.4 v capacitance 2 c a f = 1 mhz, en = 0, see figure 34 9 pf leakage current i la, hi-z v a = 0 v/v cca , en = 0, see figure 31 1 a y side input high voltage 2 v ihy v ccy ? 0.4 v input low voltage 2 v ily 0.4 v output high voltage v ohy v a = v cca , i oh = 20 a, see figure 30 v ccy ? 0.4 v output low voltage v oly v a = 0 v, i ol = 20 a, see figure 30 0.4 v capacitance 2 c y f = 1 mhz, en = 0, see figure 35 6 pf leakage current i ly, h i-z v y = 0 v/v ccy , en = 0, see figure 32 1 a enable (en) input high voltage 2 v ihen v cca = 1.15 v v cca ? 0.3 v v ihen v cca = 1.2 v to 5.5 v v cca ? 0.4 v input low voltage 2 v ilen 0.4 v leakage current i len v en = 0 v/v cca , v a = 0 v, see figure 33 1 a capacitance 2 c en 3 pf enable time 2 t en r s = r t = 50 , v a = 0 v/v cca (a y), v y = 0 v/v ccy (y a), see figure 36 1 1.8 s switching characteristics 2 3.3 v 0.3 v v cca v ccy , v ccy = 5 v 0.5 v a y level translation r s = r t = 50 , c l = 50 pf, see figure 37 propagation delay t p, a y 6 10 ns rise time t r, ay 2 3.5 ns fall time t f, a y 2 3.5 ns maximum data rate d max, a y 50 mbps channel-to-channel skew t skew, a y 2 4 ns part-to-part skew t ppskew, a y 3 ns y a level translation r s = r t = 50 , c l = 15 pf, see figure 38 propagation delay t p, y a 4 7 ns rise time t r, y a 1 3 ns fall time t f, y a 3 7 ns maximum data rate d max, y a 50 mbps channel-to-channel skew t skew, y a 2 3.5 ns part-to-part skew t ppskew, y a 2 ns
adg3304 rev. b | page 4 of 20 b version 1 parameter symbol test conditions/comments min typ max unit 1.8 v 0.15 v v cca v ccy , v ccy = 3.3 v 0.3 v a y translation r s = r t = 50 , c l = 50 pf, see figure 37 propagation delay t p, a y 8 11 ns rise time t r, ay 2 5 ns fall time t f, a y 2 5 ns maximum data rate d max, a y 50 mbps channel-to-channel skew t skew, a y 2 4 ns part-to-part skew t ppskew, a y 4 ns y a translation r s = r t = 50 , c l = 15 pf, see figure 38 propagation delay t p, y a 5 8 ns rise time t r, y a 2 3.5 ns fall time t f, y a 2 3.5 ns maximum data rate d max, y a 50 mbps channel-to-channel skew t skew, y a 2 3 ns part-to-part skew t ppskew, y a 3 ns 1.15 v to 1.3 v v cca v ccy , v ccy = 3.3 v 0.3 v a y translation r s = r t = 50 , c l = 50 pf, see figure 37 propagation delay t p, a y 9 18 ns rise time t r, ay 3 5 ns fall time t f, a y 2 5 ns maximum data rate d max, a y 40 mbps channel-to-channel skew t skew, a y 2 5 ns part-to-part skew t ppskew, a y 10 ns y a translation r s = r t = 50 , c l = 15 pf, see figure 38 propagation delay t p, y a 5 9 ns rise time t r, y a 2 4 ns fall time t f, y a 2 4 ns maximum data rate d max, y a 40 mbps channel-to-channel skew t skew, y a 2 4 ns part-to-part skew t ppskew, y a 4 ns 1.15 v to 1.3 v v cca v ccy , v ccy = 1.8 v 0.3 v a y translation r s = r t = 50 , c l = 50 pf, see figure 37 propagation delay t p, a y 12 25 ns rise time t r, ay 7 12 ns fall time t f, a y 3 5 ns maximum data rate d max, a y 25 mbps channel-to-channel skew t skew, a y 2 5 ns part-to-part skew t ppskew, a y 15 ns
adg3304 rev. b | page 5 of 20 b version 1 parameter symbol test conditions/comments min typ max unit y a translation r s = r t = 50 , c l = 15 pf, see figure 38 propagation delay t p, y a 14 35 ns rise time t r, y a 5 16 ns fall time t f, y a 2.5 6.5 ns maximum data rate d max, y a 25 mbps channel-to-channel skew t skew, y a 3 6.5 ns part-to-part skew t ppskew, y a 23.5 ns 2.5 v 0.2 v v cca v ccy , v ccy = 3.3 v 0.3 v a y translation r s = r t = 50 , c l = 50 pf, see figure 37 propagation delay t p, a y 7 10 ns rise time t r, ay 2.5 4 ns fall time t f, a y 2 5 ns maximum data rate d max, a y 60 mbps channel-to-channel skew t skew, a y 1.5 2 ns part-to-part skew t ppskew, a y 4 ns y a translation r s = r t = 50 , c l = 15 pf, see figure 38 propagation delay t p, y a 5 8 ns rise time t r, y a 1 4 ns fall time t f, y a 3 5 ns maximum data rate d max, y a 60 mbps channel-to-channel skew t skew, y a 2 3 ns part-to-part skew t ppskew, y a 3 ns power requirements power supply voltages v cca v cca v ccy 1.15 5.5 v v ccy 1.65 5.5 v quiescent power supply current i cca v a = 0 v/v cca , v y = 0 v/v ccy , v cca = v ccy = 5.5 v, en = 1 0.17 5 a i ccy v a = 0 v/v cca , v y = 0 v/v ccy , v cca = v ccy = 5.5 v, en = 1 0.27 5 a three-state mode power supply current i hi-z, a v cca = v ccy = 5.5 v, en = 0 0.1 5 a i hi-z, y v cca = v ccy = 5.5 v, en = 0 0.1 5 a 1 temperature range is as follows: b version: ?40c to +85c for the tssop and lfcsp; ?25c to +85c for the wlcsp. 2 guaranteed by design, not production tested.
adg3304 rev. b | page 6 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 2. parameter rating v cca to gnd ?0.3 v to +7 v v ccy to gnd v cca to +7 v digital inputs (a) ?0.3 v to (v cca + 0.3 v) digital inputs (y) ?0.3 v to (v ccy + 0.3 v) en to gnd ?0.3 v to +7 v operating temperature range extended industrial (b version) tssop and lfcsp ?40c to +85c industrial (b version) wlcsp ?25c to +85c storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance (4-layer board) 14-lead tssop 89.21c/w 12-ball wlcsp 120c/w 20-lead lfcsp 30.4c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
adg3304 rev. b | page 7 of 20 pin configurations and function descriptions 04860-002 1 2 3 4 5 6 7 nc = no connect a1 a2 a3 gnd nc a4 v cca 14 13 12 11 10 9 8 y1 y2 y3 en nc y4 v ccy top view (not to scale) adg3304 b a ll a1 indicator top view (balls at the bottom) not to scale y1 v ccy y2 y3 y4 gnd a1 a2 a3 a4 v cca en 04860-003 abc 1 2 3 4 pin 1 indicator nc = no connect 1nc 2a2 3a3 4a4 5nc 13 y3 14 y2 15 nc 12 y4 11 nc 6 n c 7 n c 8 g n d 1 0 n c 9 e n 1 8 v c c y 1 9 v c c a 2 0 a 1 1 7 y 1 1 6 n c top view (not to scale) adg3304 04860-057 notes 1. the exposed paddle can be tied to gnd or left floating. do not tie it to v cca or v ccy. figure 2. 14-lead tssop pin configuration figure 3. 12-ball wlcsp pin configuration figure 4. 20-lead lfcsp_vq pin configuration table 3. 14-lead tssop and 20-lead lfcsp pin function descriptions pin no. tssop lfcsp mneonic description 1 19 v cca power supply voltage input for the a1 to a4 i/o pins (1.15 v v cca v ccy ). 2 20 a1 input/output a1. referenced to v cca . 3 2 a2 input/output a2. referenced to v cca . 4 3 a3 input/output a3. referenced to v cca . 5 4 a4 input/output a4. referenced to v cca . 6, 9 1, 5, 6, 7, 10, 11, 15, 16 nc no connect. 7 8 gnd ground. 8 9 en active high enable input. 10 12 y4 input/output y4. referenced to v ccy . 11 13 y3 input/output y3. referenced to v ccy . 12 14 y2 input/output y2. referenced to v ccy . 13 17 y1 input/output y1. referenced to v ccy . 14 18 v ccy power supply voltage input for the y1 to y4 i/o pins (1.65 v v cc 5.5 v). table 4. 12-ball wlcsp pin function descriptions bup no. mneonic description a1 y1 input/output y1. referenced to v ccy . a2 y2 input/output y2. referenced to v ccy . a3 y3 input/output y3. referenced to v ccy . a4 y4 input/output y4. referenced to v ccy . b1 v ccy power supply voltage input for the y1 to y4 i/o pins (1.65 v v cc 5.5 v). b2 v cca power supply voltage input for the a1 to a4 i/o pins (1.15 v v cca v ccy ). b3 en active high enable input. b4 gnd ground. c1 a1 input/output a1. referenced to v cca . c2 a2 input/output a2. referenced to v cca . c3 a3 input/output a3. referenced to v cca . c4 a4 input/output a4. referenced to v cca .
adg3304 rev. b | page 8 of 20 typical performance characteristics 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 25 30 35 40 45 50 data rate (mbps) t a = 25c 1 channel c l = 50pf v cca = 1.8v, v ccy = 3.3v v cca = 1.2v, v ccy = 1.8v v cca = 3.3v, v ccy = 5v i cca (ma) 04860-004 figure 5. i cca vs. data rate (a y level translation) 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40 45 50 data rate (mbps) t a = 25c 1 channel c l = 50pf v cca = 1.8v, v ccy = 3.3v v cca = 1.2v, v ccy = 1.8v v cca = 3.3v, v ccy = 5v i ccy (ma) 04860-005 figure 6. i ccy vs. data rate (a y level translation) 0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 45 50 data rate (mbps) i cca (ma) t a = 25c 1 channel c l = 15pf v cca = 1.8v, v ccy = 3.3v v cca = 1.2v, v ccy = 1.8v v cca = 3.3v, v ccy = 5v 04860-006 figure 7. i cca vs. data rate (y a level translation) 0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 45 50 data rate (mbps) i ccy (ma) t a = 25c 1 channel c l = 15pf v cca = 1.8v, v ccy = 3.3v v cca = 1.2v, v ccy = 1.8v v cca = 3.3v, v ccy = 5v 04860-007 figure 8. i ccy vs. data rate (y a level translation) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 13 23 33 43 53 63 73 capacitive load (pf) i ccy (ma) 04860-012 20mbps 10mbps 5mbps 1mbps t a =25c 1 channel v cca = 1.2v v ccy = 1.8v figure 9. i ccy vs. capacitive load at pin y for a y (1.2 v 1.8 v) level translation 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 13 23 33 43 53 capacitive load (pf) i cca (ma) 04860-013 20mbps 10mbps 5mbps 1mbps t a = 25c 1 channel v cca = 1.2v v ccy =1.8v figure 10. i cca vs. capacitive load at pin a for y a (1.8 v 1.2 v) level translation
adg3304 rev. b | page 9 of 20 0 1 2 3 4 5 6 7 8 9 i ccy (ma) 13 23 33 43 53 63 73 capacitive load (pf) 04865-016 t a = 25c 1 channel v cca = 1.8v v ccy = 3.3v 30mbps 20mbps 10mbps 5mbps 50mbps figure 11. i ccy vs. capacitive load at pin y for a y (1.8 v 3.3 v) level translation 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 i cca (ma) 13 23 33 43 53 capacitive load (pf) 04860-017 50mbps t a = 25c 1 channel v cca = 1.8v v ccy = 3.3v 5mbps 10mbps 20mbps 30mbps figure 12. i cca vs. capacitive load at pin a for y a (3.3 v 1.8 v) level translation 0 2 4 6 8 10 12 i ccy (ma) 13 23 33 43 53 63 73 capacitive load (pf) 04860-020 t a = 25c 1 channel v cca = 3.3v v ccy = 5v 50mbps 30mbps 20mbps 10mbps 5mbps figure 13. i ccy vs. capacitive load at pin y for a y (3.3 v 5 v) level translation 0 2 4 6 i cca (ma) 13 23 33 43 53 capacitive load (pf) 04860-021 t a = 25c 1 channel v cca = 3.3v v ccy = 5v 50mbps 30mbps 20mbps 10mbps 5mbps 1 3 5 7 figure 14. i cca vs. capacitive load at pin a for y a (5 v 3.3 v) level translation 0 1 2 3 4 5 6 7 8 9 10 13 23 33 43 53 63 73 capacitive load (pf) rise time (ns) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 04860-023 figure 15. rise time vs. capacitive load at pin y (a y level translation) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 13 23 33 43 53 63 73 capacitive load (pf) fall time (ns) t a = 25c 1 channel data rate = 50kbps v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v v cca = 1.2v, v ccy = 1.8v 04860-024 figure 16. fall time vs. capacitive load at pin y (a y level translation)
adg3304 rev. b | page 10 of 20 0 1 2 3 4 5 6 7 8 9 10 13 18 23 28 33 38 43 48 53 rise time (ns) capacitive load (pf) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 04860-025 figure 17. rise time vs. capacitive load at pin a (y a level translation) 13 18 23 28 33 38 43 48 53 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fall time (ns) capacitive load (pf) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 04860-026 figure 18. fall time vs. capacitive load at pin a (y a level translation) 0 2 4 6 8 10 12 14 13 23 33 43 53 63 73 capacitive load (pf) propagation delay (ns) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 04860-027 figure 19. propagation delay (t plh ) vs. capacitive load at pin y (a y level translation) 04860-028 0 2 4 6 8 10 12 13 23 33 43 53 63 73 propagation delay (ns) capacitive load (pf) data rate = 50kbps t a = 25c 1 channel v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v figure 20. propagation delay (t phl ) vs. capacitive load at pin y (a y level translation) 0 1 2 3 4 5 6 7 8 9 13 18 23 28 33 38 43 48 53 capacitive load (pf) propagation delay (ns) t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v 04860-029 figure 21. propagation delay (t plh ) vs. capacitive load at pin a (y a level translation) 0 1 2 3 4 5 6 7 8 9 13 18 23 28 33 38 43 48 53 capacitive load (pf) propagation delay (ns) 04860-030 t a = 25c 1 channel data rate = 50kbps v cca = 1.2v, v ccy = 1.8v v cca = 1.8v, v ccy = 3.3v v cca = 3.3v, v ccy = 5v figure 22. propagation delay (t phl ) vs. capacitive load at pin a (y a level translation)
adg3304 rev. b | page 11 of 20 t a = 25c data rate = 25mbps c l = 50pf 1 channel 5ns/div 04860-037 400mv/div figure 23. eye diagram at y output (1.2 v to 1.8 v level translation, 25 mbps) 5ns/div 04860-038 200mv/div t a = 25c data rate = 25mbps c l = 50pf 1 channel figure 24. eye diagram at a output (1.8 v to 1.2 v level translation, 25 mbps) t a = 25c data rate = 50mbps 3ns/div 04860-039 500mv/div c l = 50pf 1 channel figure 25. eye diagram at y output (1.8 v to 3.3 v level translation, 50 mbps) t a = 25c data rate = 50mbps c l = 15pf 1 channel 3ns/div 04860-040 400mv/div figure 26. eye diagram at a output (3.3 v to 1.8 v level translation, 50 mbps) t a = 25c data rate = 50mbps cl = 50pf 1 channel 3ns/div 04860-041 1v/div figure 27. eye diagram at y output (3.3 v to 5 v level translation, 50 mbps) t a = 25c data rate = 50mbps c l = 15pf 1 channel 3ns/div 04860-042 800mv/div figure 28. eye diagram at a output (5 v to 3.3 v level translation, 50 mbps)
adg3304 rev. b | page 12 of 20 test circuits adg3304 a y gnd v cca v ccy en k1 k2 i oh i ol 04860-043 0.1 f 0.1 f figure 29. v oh /v ol voltages at pin a adg3304 y a gnd v ccy v cca en k1 k2 i oh i ol 04860-044 0.1 f 0.1 f figure 30. v oh /v ol voltages at pin y adg3304 a y gnd v cca v ccy k 04860-045 0.1 f 0.1 f a en figure 31. three-state leakage current at pin a adg3304 a y gnd v cca v ccy k 04860-046 0.1 f 0.1 f en a figure 32. three-state leakage current at pin y adg3304 a y gnd v cca v ccy k 04860-047 0.1 f 0.1 f en a figure 33. en pin leakage current adg3304 a y gnd v cca v ccy en 04860-048 capacitance meter figure 34. capacitance at pin a
adg3304 rev. b | page 13 of 20 04860-049 adg3304 a y gnd v cca v ccy en capacitance meter figure 35. capacitance at pin y 90% v en v y /v a t en1 v a /v y v cca 0v v cca /v ccy 0v v ccy /v cca 0v 10% v en v y /v a t en2 v a /v y v cca 0v 0v v ccy /v cca 0v notes 1. t en is whichever is larger between t en1 and t en2 in both a y and y a directions. signal source v en r t 50 v a adg3304 en gnd r s 50 0.1 f v cca a 1m v y 50pf 1m v ccy y k2 04860-050 z 0 = 50 k1 10 f + 0.1 f 10 f + a y direction signal source v en r t 50 1m v a 15pf adg3304 en gnd r s 50 0.1 f 1m v cca a v y v ccy y k2 z 0 = 50 k1 10 f + 0.1 f 10 f + y a direction v cca /v ccy figure 36. enable time
adg3304 rev. b | page 14 of 20 50% 50% 10% 90% v a v y t f,a y t r,a y t p,a y t p,a y adg3304 gnd signal source v a r t 50 r s 50 en v cca v ccy v y 50pf 04860-051 z 0 = 50 ya 0.1 f 10 f + 0.1 f 10 f + figure 37. switching characteristics (a y level translation) 50% 50% 10% 90% v y v a t f,y a t r,y a t p,y a t p,y a adg3304 gnd signal source v y r t 50 r s 50 en v cca v ccy v a 15pf 04860-052 z 0 = 50 ya 0.1 f 10 f + 0.1 f 10 f + figure 38. switching characteristics (y a level translation)
adg3304 rev. b | page 15 of 20 terminology v iha logic input high voltage at pin a1 to pin a4. v ila logic input low voltage at pin a1 to pin a4. v oha logic output high voltage at pin a1 to pin a4. v ola logic output low voltage at pin a1 to pin a4. c a capacitance measured at pin a1 to pin a4 (en = 0). i la, hi-z leakage current at pin a1 to pin a4 when en = 0 (high impedance state at pin a1 to pin a4). v ihy logic input high voltage at pin y1 to pin y4. v ily logic input low voltage at pin y1 to pin y4. v ohy logic output high voltage at pin y1 to pin y4. v oly logic output low voltage at pin y1 to pin y4. c y capacitance measured at pin y1 to pin y4 (en = 0). i ly, hi-z leakage current at pin y1 to pin y4 when en = 0 (high impedance state at pin y1 to pin y4). v ihen logic input high voltage at the en pin. v ilen logic input low voltage at the en pin. c en capacitance measured at en pin. i len enable (en) pin leakage current. t en three-state enable time for pin a1 to pin a4 and pin y1 to pin y4. t p, a y propagation delay when translating logic levels in the ay direction. t r, ay rise time when translating logic levels in the ay direction. t f, ay fall time when translating logic levels in the ay direction. d max, ay guaranteed data rate when translating logic levels in the ay direction under the driving and loading conditions specified in table 1 . t skew, ay difference between propagation delays on any two channels when translating logic levels in the ay direction. t ppskew, ay difference in propagation delay between any one channel and the same channel on a different part (under same driving/ loading conditions) when translating in the ay direction. t p, y a propagation delay when translating logic levels in the ya direction. t r, ya rise time when translating logic levels in the ya direction. t f, ya fall time when translating logic levels in the ya direction. d max, ya guaranteed data rate when translating logic levels in the ya direction under the driving and loading conditions specified in table 1 . t skew, ya difference between propagation delays on any two channels when translating logic levels in the ya direction. t ppskew, ya difference in propagation delay between any one channel and the same channel on a different part (under the same driving/ loading conditions) when translating in the ya direction. v cca v cca supply voltage. v ccy v ccy supply voltage. i cca v cca supply current. i ccy v ccy supply current. i hi-z, a v cca supply current during three-state mode (en = 0). i hi-z, y v ccy supply current during three-state mode (en = 0).
adg3304 rev. b | page 16 of 20 theory of operation the adg3304 level translator allows the level shifting necessary for data transfer in a system where multiple supply voltages are used. the device requires two supplies, v cca and v ccy (v cca v ccy ). these supplies set the logic levels on each side of the device. when driving the a pins, the device translates the v cca -compatible logic levels to v ccy -compatible logic levels available at the y pins. similarly, because the device is capable of bidirectional translation, when driving the y pins, the v ccy - compatible logic levels are translated to v cca -compatible logic levels available at the a pins. when en = 0, pin a1 to pin a4 and pin y1 to pin y4 are three-stated. when en is driven high, the adg3304 goes into normal operation mode and performs level translation. level translator architecture the adg3304 consists of four bidirectional channels. each channel can translate logic levels in either the ay or the ya direction. it uses a one-shot accelerator architecture, which ensures excellent switching characteristics. figure 39 shows a simplified block diagram of a bidirectional channel. one-shot generator 6k 6k y v cca v ccy t2 t1 t3 t4 a 04860-053 p n u1 u2 u4 u3 figure 39. simplified block diagram of an adg3304 channel the logic level translation in the ay direction is performed using a level translator (u1) and an inverter (u2), while the translation in the ya direction is performed using inverter u3 and inverter u4. the one-shot generator detects a rising or falling edge present on either the a side or the y side of the channel. it sends a short pulse that turns on the pmos transistors (t1 to t2) for a rising edge, or the nmos transistors (t3 to t4) for a falling edge. this charges/discharges the capacitive load faster, which results in faster rise and fall times. the inputs of the unused channels (a or y) should be tied to their corresponding v cc rail (v cca or v ccy ) or to gnd. input driving requirements to ensure correct operation of the adg3304, the circuit that drives the input of the adg3304 channels should have an output impedance of less than or equal to 150 and a minimum peak current driving capability of 36 ma. output load requirements the adg3304 level translator is designed to drive cmos- compatible loads. if current-driving capability is required, it is recommended to use buffers between the adg3304 outputs and the load. enable operation the adg3304 provides three-state operation at the a and y i/o pins by using the enable pin (en), as shown in table 5 . table 5. truth table en y i/o pins a i/o pins 0 hi-z 1 hi-z 1 1 normal operation 2 normal operation 2 1 high impedance state. 2 in normal operation, the ad g3304 performs level translation. while en = 0, the adg3304 enters into three-state mode. in this mode, the current consumption from both the v cca and v ccy supplies is reduced, allowing the user to save power, which is critical, especially on battery-operated systems. the en input pin can be driven with either v cca -compatible or v ccy -compatible logic levels. power supplies for proper operation of the adg3304, the voltage applied to the v cca must be less than or equal to the voltage applied to v ccy . to meet this condition, the recommended power-up sequence is v ccy first and then v cca . the adg3304 operates properly only after both supply voltages reach their nominal values. it is not recommended to use the part in a system where, during power-up, v cca can be greater than v ccy due to a significant increase in the current taken from the v cca supply. for optimum performance, the v cca pin and v ccy pin should be decoupled to gnd as close as possible to the device.
adg3304 rev. b | page 17 of 20 data rate the maximum data rate at which the device is guaranteed to operate is a function of the v cca and v ccy supply voltage combination and the load capacitance. it is given by the maximum frequency of a square wave that can be applied to the device, which meets the v oh and v ol levels at the output and does not exceed the maximum junction temperature (see the absolute maximum ratings section). tabl e 6 shows the guaranteed data rates at which the adg3304 can operate in both directions (ay or ya level translation) for various v cca and v ccy supply combinations. table 6. guaranteed data rate (mbps) 1 v ccy v cca 1.8 v (1.65 v to 1.95 v) 2.5 v (2.3 v to 2.7 v) 3.3 v (3.0 v to 3.6 v) 5 v (4.5 v to 5.5 v) 1.2 v (1.15 v to 1.3 v) 25 30 40 40 1.8 v (1.65 v to 1.95 v) - 45 50 50 2.5 v (2.3 v to 2.7 v) - - 60 50 3.3 v (3.0 v to 3.6 v) - - - 50 5 v (4.5 v to 5.5 v) - - - - 1 the load capacitance used is 50 pf when translating in the a y direction and 15 pf when translating in the y a direction.
adg3304 rev. b | page 18 of 20 applications the adg3304 is designed for digital circuits that operate at different supply voltages; therefore, logic level translation is required. the lower voltage logic signals are connected to the a pins, and the higher voltage logic signals are connected to the y pins. the adg3304 can provide level translation in both directions from ay or ya on all four channels, eliminating the need for a level translator ic for each direction. the internal architecture allows the adg3304 to perform bidirectional level translation without an additional signal to set the direction in which the translation is made. it also allows simultaneous data flow in both directions on the same part, for example, when two channels translate in ay direction while the other two translate in ya direction. this simplifies the design by eliminating the timing requirements for the direction signal and reducing the number of ics used for level translation. figure 40 shows an application where two microprocessors operating at 1.8 v and 3.3 v, respectively, can transfer data simultaneously using two full-duplex serial links, tx1/rx1 and tx2/rx2. v ccy y1 y2 y3 y4 en gnd a4 a3 a2 a1 v cca adg3304 microprocessor/ microcontroller/ dsp 1.8v 3.3v microprocessor/ microcontroller/ dsp 100nf 100nf tx1 rx2 tx2 rx1 rx1 tx2 rx2 tx1 gnd 04860-056 gnd figure 40. 1.8 v to 3.3 v level translation circuit on two full-duplex serial links when the application requires level translation between a micro- processor and multiple peripheral devices, the adg3304 i/o pins can be three-stated by setting en = 0. this feature allows the adg3304 to share the data buses with other devices without causing contention issues. figure 41 shows an application where a 1.8 v microprocessor is connected to a 3.3 v peripheral device using the three-state feature. v ccy y1 y2 y3 y4 en gnd a4 a3 a2 a1 v cca adg3304 microprocessor/ microcontroller/ dsp cs 1.8v 3.3v peripheral device 1 100nf 100nf i/o l1 i/o l4 i/o l3 i/o l2 i/o h1 i/o h4 i/o h3 i/o h2 gnd 04860-055 100nf 100nf gnd v ccy y1 y2 y3 y4 en gnd a4 a3 a2 a1 v cca adg3304 3.3v peripheral device 2 i/o h1 i/o h4 i/o h3 i/o h2 gnd figure 41. 1.8 v to 3.3 v level translation circuit using the three-state feature layout guidelines as with any high speed digital ic, the printed circuit board layout is important for the overall performance of the circuit. care should be taken to ensure proper power supply bypass and return paths for the high speed signals. each v cc pin (v cca and v ccy ) should be bypassed using low effective series resistance (esr) and effective series inductance (esi) capacitors placed as close as possible to the v cca pin and the v ccy pin. the parasitic inductance of the high speed signal track may cause significant overshoot. this effect can be reduced by keeping the length of the tracks as short as possible. a solid copper plane for the return path (gnd) is also recommended.
adg3304 rev. b | page 19 of 20 outline dimensions 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 coplanarity 0.10 compliant to jedec standards mo-153-ab-1 figure 42. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters seating plane 0.50 bsc ball pitch 1.67 1.61 1.55 0.28 0.24 0.20 0.17 0.15 0.13 0.36 0.32 0.28 0.65 0.59 0.53 bottom view (ball side up) 2.07 2.01 1.95 top view (ball side down) 1 a b c 2 3 4 ball 1 identifier 111105-0 figure 43. 12-ball wafer level chip scale package [wlcsp] (cb-12) dimensions shown in millimeters 1 20 5 6 11 16 15 10 2.25 2.10 sq 1.95 0.75 0.55 0.35 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicato r top view 3.75 bcs sq 4.00 bsc sq coplanarity 0.08 0.60 max 0.60 max 0.25 min compliant to jedec standards mo-220-vggd-1 pin 1 indicator figure 44. 20-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-20-1) dimensions shown in millimeters
adg3304 rev. b | page 20 of 20 ordering guide model temperature range package description branding 1 package option ADG3304BRUZ 2 ?40c to +85c 14-lead thin shrink small outline package [tssop] ru-14 ADG3304BRUZ-reel 2 ?40c to +85c 14-lead thin shrink small outline package [tssop] ru-14 ADG3304BRUZ-reel7 2 ?40c to +85c 14-lead thin shrink small outline package [tssop] ru-14 adg3304bcpz-reel 2 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 adg3304bcpz-reel7 2 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 adg3304bcbz-reel 2 ?25c to +85c 12-ball wafer level chip scale package [wlcsp] sdc cb-12 adg3304bcbz-reel7 2 ?25c to +85c 12-ball wafer level chip scale package [wlcsp] sdc cb-12 1 branding on these packages is limited to three characters due to space constraints. 2 z = pb-free part. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04860-0-12/05(b)

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